INTRODUCTION

Generally, the life of a device would decrease to half, and the failure rate would double whenever Junction Temperature, Tj, goes up by 10°C. Moreover, when Tj exceeds 175°C, a device has the possibility of breaking.Therefore, it is necessary to keep Tj in the proper temperature range, which is the lower the better, and a heat design should be done under the condition of the range of 80-100℃.In fact, it is difficult for IC packages that handle high power to keep Tj in this range. Therefore, it is common to make Tj the 80% of a maximum permissible temperature.A value of a thermal resistance is dependent on a chip, a layout of a leadframe, a board, and so forth. It means even if sizes of the IC packages are the same and layouts of leadframes are different, thermal resistances are not the same.

DEFINITIONS

The thermal resistance of a IC package is calculated by the difference between Tj and the ambient Temperature, Ta, under the condition that the IC package dissipates electric power of 1W. Here are three expressions of the thermal resistance, and each term of expressions are defined in Table1 and Fig.1.

Thermal resistances
Thermal resistancesFig.1 Thermal resistances of a IC package
Table1 Definitions
Item Definitions
θja thermal resistance between Tj and Ta
ψjt thermal resistance between Tj and Tc1
θjc thermal resistance between Tj and Tc2
θca thermal resistance between Tc and Ta
Tj junction temperature
Ta ambient temperature
Tc1 temperature of the top surface of IC package
Tc2 temperature of the bottom surface of IC package
Pd maximum permissible power

Estimation of Tj when ψjt is known

Tj can be estimated by following order

  1. Power, P, is calculated by operating current and voltage.
  2. Tc1 is measured by using a thermometer like a radiation thermometer and thermocouples.
  3. Tj is calculated by Tc1, and ψjt which is shown in Table 3.

Tj=ψjt×P + Tc1Note) θja and ψjt in Table 3 are measured values based on JEDEC with no wind.Each value is dependent on a chip, a layout of a leadframe, a board, and so forth.

Measurement of Thermal Resistance

The measurement of thermal resistance is based on JEDEC.

[Test board]The outline of the measurement board is shown in Fig.2, which is based on JEDEC.

Measurement boardFig.2 Measurement board

Note)

  • Board material : FR-4
  • Board dimension:
    • ( 2-layer board ) 114.3x76.2mm,Thickness 1.57mm
    • ( 4-layer board with Cu foil 1,2 ) 114.3x76.2mm,Thickness 1.6mm
  • Cu foil dimension : 74.2x74.2mm (Thickness 35µm) are applied to 4-layer board, as Cu foil 1, 2.
[Chip for measurement of Thermal Resistance]A chip is composed of elements of a resistance and a diode. The resistance is used for heating, and the diode is for a sensor of temperature. We have three kinds of size, because thermal resistance is dependent on a chip size.

Image of the chipFig.3 Image of the chip
[Measurement of K factor]Tj cannot be measured directly. However, by a character of a forward voltage, V F of a diode is dependent on temperature. Therefore, Tj is known during a measurement by measuring VF.However, dependency of diode which called K-factor, K, should be measured first.

K-factor
[JEDEC chamber]

  • JEDEC chamber with no wind condition (still air) is adopted.The ambient temperature is measured with thermocouples at the position that is located 25.4mm below the center of the IC package.
  • JEDEC chamberFig.4 JEDEC chamber
[Measurement circuit]Measurement circuitFig.5 Measurement circuit
[Measurement procedure]

  1. VF0 is measured by giving the diode with a current (1mA), IM, at the ambient temperature.
  2. A Voltage, VH, is given to the resistance in the chip until temperature at upper surface of the IC package, which is measured with a radiation thermometer, is saturated. After confirming the saturation, IH is read.
  3. VFSS is measured by giving the diode with a current, IM.

Timing of measurementFig.6 Timing of measurement

Note) VH is measured at three points, the voltage of Tstg-max, Vstg-max, and lower and higher than Vstg-max.

[Calculation]θja an ψjt are calculated from the following Table 2.

Table 2 Thermal resistance calculationThermal resistance calculation

[The Permissible Regions of Dissipated Power]Pd is the maximum permissible power at Ta=25°C.Pd is dependent on the ambient temperture, which is shown in Fig.7.

Ambient temperatureFig.7 The maximum permissible power

Thermal Resistance of each package

There are typical measured value based on JEDEC with no wind. Each value is dependent on a chip, a layout of a leadframe, a board, and so forth.

Table 3 Thermal resistance of each package
PKG 2 layer board 4 layer board
Tj:125°C Tj:150°C Tj:125°C Tj:150°C
θja ψjt Pd@Ta=25°C θja ψjt Pd@Ta=25°C
(°C/W) (°C/W) mW (°C/W) (°C/W) mW
DMP8 235 47 425 530 175 40 570 710
DMP14 195 47 510 640 150 40 665 830
DMP16 195 47 510 640 150 40 665 830
DMP20 150 37 665 830 120 33 830 1040
SOP8 JEDEC(EMP8) 180 34 555 690 125 29 800 1000
SOP16 JEDEC(EMP16-E2) 110 21 905 1135 70 18 1425 1785
SOP8 165 26 605 755 110 23 905 1135
SOP14 125 21 800 1000 80 17 1250 1560
SOP22 120 18 830 1040 85 14 1175 1470
SOP28 155 37 645 805 125 33 800 1000
SOP40-K1 135 37 740 925 105 33 950 1190
SSOP8 270 42 370 460 210 36 475 595
SSOP8-A3 215 36 465 580 155 15 645 805
SSOP10 270 42 370 460 210 36 475 595
SSOP14 225 38 440 555 180 33 555 690
SSOP16 210 35 475 595 160 26 625 780
SSOP20 185 34 540 675 140 26 710 890
SSOP20-B2 200 34 500 625 150 26 665 830
SSOP20-C3 130 13 765 960 85 9 1175 1470
SSOP32 110 20 905 1135 70 14 1425 1785
SSOP44 110 20 905 1135 70 14 1425 1785
TSSOP54-N1 105 10 950 1190 75 9 1330 1665
HSOP82) 160 28 625 780 50 12 2000 2500
HTSSOP24-P12) 115 14 865 1085 45 7 2220 2775
MSOP8(TVSP8) 215 27 465 580 160 23 625 780
MSOP10(TVSP10) 215 27 465 580 160 23 625 780
MSOP8(VSP8) 210 33 475 595 155 25 645 805
MSOP10(VSP10) 210 33 475 595 155 25 645 805
SC-88A 355 89 280 350 260 73 380 480
SC-82AB 365 89 270 340 255 72 390 490
SOT-23-5 260 70 380 480 195 60 510 640
SOT-23-6 245 70 405 510 175 60 570 710
SOT-89-31)2) 200 67 500 625 130 65 765 960
QFP32-J2 115 17 865 1085 90 15 1110 1385
QFP44-A1 95 17 1050 1315 75 15 1330 1665
QFP48-P1 65 17 1535 1920 50 15 2000 2500
LQFP48-R3 75 9 1330 1665 45 5 2220 2775
LQFP52-H2 85 11 1175 1470 65 11 1535 1920
QFP56-A1 105 17 950 1190 80 15 1250 1560
QFP64-H1 70 17 1425 1785 50 15 2000 2500
LQFP64-H2 65 6 1535 1920 50 5 2000 2500
QFP100-U1 55 5 1815 2270 45 5 2220 2775
TO-252-31)2) 105 17 950 1190 40 12 2500 3125
PLCC28 55 10 1815 2270 35 7 2855 3570
EPFFP6-A22) 370 59 270 335 220 53 450 565
EPFFP10-C42) 295 64 335 420 160 55 625 780
PCSP12-C3 240 40 415 520 140 33 710 890
PCSP20-CC 225 40 440 555 140 33 710 890
PCSP20-E3 225 40 440 555 130 33 765 960
PCSP24-ED 205 40 485 605 115 26 865 1085
PCSP32-F7 225 24 440 555 115 17 865 1085
PCSP32-G32) 205 24 485 605 115 17 865 1085
PCSP32-GD2) 205 24 485 605 115 17 865 1085
EPCSP32-L22) 210 29 475 595 95 16 1050 1315
DFN6-J1 (SON6-J1) 345 88 285 360 260 69 380 480
DFN4-F1 (ESON4-F1)2) 300 52 330 415 110 27 905 1135
DFN6-H1 (ESON6-H1)2) 280 42 355 445 110 26 905 1135
DFN8-U1 (ESON8-U1)2) 280 43 355 440 110 26 905 1135
DFN8-V1 (ESON8-V1)2) 215 16 465 580 70 8 1425 1785
DFN8-W2 (ESON8-W2)2) 195 21 510 640 60 8 1665 2080
QFN24-T1/T2 150 22 665 830 75 15 1330 1665
EQFN12-E22) 285 52 350 435 105 27 950 1190
EQFN12-E42) 285 52 350 435 105 27 950 1190
EQFN14-D72) 295 53 335 420 95 26 1050 1315
EQFN16-G22) 255 43 390 490 100 26 1000 1250
EQFN12-JE2) 215 22 465 580 80 10 1250 1560
EQFN16-JE2) 180 21 555 690 70 11 1425 1785
EQFN18-E72) 220 33 450 565 90 22 1110 1385
EQFN26-HH2) 160 15 625 780 60 7 1665 2080
EQFN24-LK2) 145 13 685 860 65 8 1535 1920
Notes
1) Thermal resistance values (θja,ψjt) are measured with the 2-layer board having 100mm2 copper foil, which is based on JEDEC.
2) Thermal resistance values (θja,ψjt) are measured with the 4-layer board having thermal via holes, which is also based on JEDEC.

Thermal Resistance depending on area of Cu foil

There are typical values by mounting on five kinds of boards, "PAT.1" through "PAT.5", shown in Table 4 and Table 5.Those are 2-layer boards based on JEDEC. However, they do not have any thermal via holes.

Thermal Resistance depending on area of Cu foilFig.8 Thermal Resistance depending on area of Cu foilImage of Cu foilTable 4 Image of Cu foil

teble TO-252 SOT-89 SOT-23-5
SOT-23-6
PAT.1 PAT PAT PAT
PAT.2 PAT PAT PAT
PAT.3 PAT PAT PAT
PAT.4 PAT PAT PAT
PAT.5 PAT PAT -
Table 5 Image of Cu foil
PAT SC-88A
SC-82AB
PAT.1 PAT
PAT.2 PAT
PAT.3 PAT
PAT.4 PAT
Table 6 Area of Cu foil
teble TO-252 SOT-89 SOT-23-5
SOT-23-6
SC-88A
SC-82AB
PAT.1 100mm2
PAT.2 225mm2
PAT.3 400mm2
PAT.4 600mm2 1600mm2
PAT.5 1225mm2 -